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Understanding Beta

beta24

Re: Understanding Beta

Postby Alan0354 » September 28th, 2019, 11:07 pm

This is the gm graph of IRFP240, you can see from the marks, if you increase current from 100mA to 2.5A, you have to increase the Vgs about 0.9V. So the Vgs is not constant through out the cycle of the sine wave. This is always true regardless of BJT or MOSFET, just MOSFET swing more. For BJT, Vbe only change by 80mV going from 0.1A to 2.5A.

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Re: Understanding Beta

Postby Alan0354 » September 28th, 2019, 11:14 pm

Do you use LTSpice, when I have time, I'll try to simulate this to see what happen.
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Understanding Beta

Postby amb » September 29th, 2019, 11:54 am

Ah yes, the previous simulation graph I posted is kind of a macroscopic view of what happens at the MOSFET junctions so it doesn't show the small stuff that's hapenning. The MOSFETs used in the β24 are the IRFP140N and IRFP9140N, with steeper curves in its gm graph at the low end less than a few amperes than the IRFP240. Anyway here is a direct plot of Vgs using a differential voltage probe across the gate and source pins, under the same operating conditions. Vgs changes from 3.15V to 3.88V (about 0.73V total) from peak to peak of the sine wave signal cycle. This is still a small amount of change given the magnitude of the signal, and does not invalidate the effectiveness of the dynamic cascode.

Image

Below is the Vgs curve superimposed on the graph posted previously (voltages at the 3 MOSFET pins), to show relative differences:

Image

I use OrCAD Capture CIS and PSpice A/D for simulation.

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Re: Understanding Beta

Postby Alan0354 » September 29th, 2019, 2:36 pm

amb wrote:Ah yes, the previous simulation graph I posted is kind of a macroscopic view of what happens at the MOSFET junctions so it doesn't show the small stuff that's hapenning. The MOSFETs used in the β24 are the IRFP140N and IRFP9140N, with steeper curves in its gm graph at the low end less than a few amperes than the IRFP240. Anyway here is a direct plot of Vgs using a differential voltage probe across the gate and source pins, under the same operating conditions. Vgs changes from 3.15V to 3.88V (about 0.73V total) from peak to peak of the sine wave signal cycle. This is still a small amount of change given the magnitude of the signal, and does not invalidate the effectiveness of the dynamic cascode.

Image

Below is the Vgs curve superimposed on the graph posted previously (voltages at the 3 MOSFET pins), to show relative differences:

Image

I use OrCAD Capture CIS and PSpice A/D for simulation.



You beat me to it, I just did the simulation and is about to post it, you got it already. Yes, the change of Vgs and Vds is small. Actually my question to you is about what is the EQUIVALENT capacitance loading the driver stage. That's what my original post asking for your opinion. My opinion is if the Ciss = 2000pF the effective loading capacitance is about 2000pF TIMES by Vout/Vgs = 0.73/10 = 0.073. Which is 2000pF X 0.073 = 146pF. It's a lot of improvement. Below was my original post that asked your opinion:



Alan0354 wrote:Yeh, even I use BJT LTP, I use BC550 and BC560 for my complementary IPS LTP. The beta of the match pairs are too low and draw too much base current for my liking. I have to hand pick each pair. This is actually not that hard compare picking 9 matching power transistors. I have to build a fixture to put like 50 transistor on and power up at the same time to measure the Vbe to pick match batches of 9. On top, I have to take into consideration the location of the transistors on the heatsink to compensate the different temperature difference. eg. I expect the transistors at the two ends will be a little lower temperature on the heatsink, so I have to choose two that the Vbe is about 3mV lower than the ones in the middle. I buy at least 100 at a time to pick out the sets.

One think I never got it that clear, what is the effect of Cbe ( or Cgs of MOSFET) of BJT on the driver. Seems like the Stasis condition you described is only in ideal situation. In real life, you have dVgs/dId = dVgs/dVout, as Id = Vout/RL

Seems like the effect of Cgs loading effect on the driver is divided by dVgs/dVout. So say Vgs increase by 1V when the ouput swing from 0 to 30V, so dVgs/dVout = 1/30. So if Cgs= 3000pF, the equivalent loading capacitance on the driver is 3000pF/30 = 100pF. What do you think? I have not seen anyone one or any book that talk about this.
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Re: Understanding Beta

Postby amb » September 29th, 2019, 5:05 pm

Yes, except for the IRFP140N, Ciss is 1400pF, not 2000pF, so the equivalent loading is even lower at 102pF. Pretty good for a big MOSFET.
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Re: Understanding Beta

Postby Alan0354 » September 29th, 2019, 6:30 pm

Max Vds is only 100V, that's cutting it very close. I choose transistors that are 200V, so I can have the option to run at +/-70V. That's how it is, there's a lot of low voltage transistors that have better gm, lower capacitor, better spec. But if you get to higher voltage, that's where the challenges are.

In a way, differential output is a double edge sword. Yes, you can get higher power with lower rail voltage. But remember the load impedance is HALVED. Say if you use 8ohm speakers, the load presented to the output of each side of the differential amp is 4ohm. It's half the impedance of the speaker. This literally give you twice the load capacitance on the driving stage. THD literally double when load impedance is halved, That's life. It's a lot to consider. That's the reason I still have not try the full differential circuit. I still have to weight the advantage when I have to double the amount of circuits to do differential output OR optimize the single end circuit.
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Re: Understanding Beta

Postby amb » September 29th, 2019, 7:54 pm

All true. That’s the reason the β24 was designed the way it is, optimized by cascoding all stages, and other fine touches.
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Re: Understanding Beta

Postby Alan0354 » September 29th, 2019, 11:27 pm

I think we are drifting too far from my question. My question is whether it is correct to look at the effective loading capacitance equals to the Ciss X (Vgs/Vout)? eg, in your case, the effective loading is only 102pF instead of 1400pF.

This is only my guessing, I never read anything in books talking about this. I want to see whether you read anything on this. Most of them talk about MOSFET(even BJT) in common Source ( emitter) configuration as most commonly used of MOSFET is for SMPS. We are using it as source follower and the source is swinging with the input.

The effect is even worst for BJT as the Cbe increase with emitter current, when getting into a few amps, the Cbe can be up to over 0.1uF!!! That is shown in the book of Bob Cordell.

I want to make sure I am correct on this.

Thanks
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Re: Understanding Beta

Postby amb » September 30th, 2019, 9:22 am

Good question. I thought you knew the answer rather than posting it as a question, so I went along with it. Sounded reasonable to me but I’m not certain!

Indeed most articles and books (and there are many) that have coverage on cascoding and input capacitance reduction mention the Miller effect, and use common emitter/source topology for analysis. That is obviously not the topology of what we have at the output stage. I recall that when I was doing research on this when designing the β22 amp, I did a lot of reading on this, and I did find something of relevance that helped, but I don’t remember where or what it was. That was over 10 years ago.

Nevertheless the benefits of cascoding is real, in common emitter/source or common collector/drain topologies, not just in terms of junction capacitance reduction, but also in other ways too, such as distortion reduction. Rather than relying on calculation, I see these in action with simulation and with measuring actual circuit prototypes.
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Re: Understanding Beta

Postby Alan0354 » September 30th, 2019, 2:20 pm

No, I don't know the answer, I was hoping you being an amp designer might have run across it. I am purely guessing based on common sense. In fact I mainly interested in Cbe ( Cgs in your case). BJT usually have much lower Cbc ( Cgd) and it's really not a problem and don't think there is advantage doing the cascode with BJT output stage. Cgd of MOSFET is really high, that would present a problem and you did the right thing using cascode. Cbe is very high on BJT running at high current, that's where my concern is.

Speaking of that, you might get better result using BJT as cascode transistor Q37 and Q38. The reason change of Vbe is much smaller than MOSFET. Change of Vbe from 0.1A to 2.5A current is only about 80mV compare to 730mV change of Vgs that you observe. It's almost 10 times smaller, that will reduce the effect of capacitance loading of Cgd of Q33 and Q34. If I am right about the capacitance, you reduce the effective capacitance from 102pF by almost half or so if you use BJT for Q37 & Q38.( the reason Ciss = Cgs+Cgd. Using BJT on Q37 and Q38 reduce only the effect of Cgd, the effect of Cgs remains untouched). Q33 and Q34 are still MOSFET, you still maintain the goodness of the MOSFET OPS. Also, Vbe is only 0.6V or so compare to Vgs of 4V. You gain over 3V of headroom on the power supply.......less heat, using lower voltage to get the same output. I don't even think you have to change pcb or anything, those BJT are pin to pin compatible with the MOSFETs. I don't think you need to change anything else for it to work. Of cause you can change the Zener diode voltage and lower the supply voltage to reduce the heat.
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