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Understanding Beta

beta24

Understanding Beta

Postby BesPav » January 15th, 2017, 9:19 pm

In post #6 i have to show Beta22 VAS.
Discerning one can ask - why we can't use both shoulders of this stage?
Stage have intrinsic symmetry, which are disrupted by using one half to detect and neutralise shift from ground.

Now Ti have published Beta24's schematic and we can see that profound and wise decision:

CMFB circuitry controls the centerpoint of output voltage by sensing it at left half and comparing with ground voltage in the right half:
Image

Output of this stage - are current, that flows through VAS (i have drawn positive and negative paths in different shoulders, but you must understand, that regulatory current flows in both shoulders in the same direction)
Image

Now, we have voltage drop of the regulatory current in the needed reference points!

Bravo, Ti!
Simple, but very sophisticated!
Easy, but very elegant!

Now, we have our signal amplified in the VAS stage and simultaneously VAS stage deducts common-mode noise.



Something similar can be drawn like this:
Image
But, you can be shure, you would be unable to provide proper correstion for shown circuit, even if you are familiar with that technique.
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Re: Understanding Beta

Postby BesPav » January 16th, 2017, 8:54 am

Now, we are more or less understanding Beta24's conception and schematic decisions.
Let's see to practical realisation - PCB.

I've take photo from one of the forum threads.
Image

Huge magenta circle are showing (and limits) small-signal part of the amplifier, IPS and VAS stages.
Magenta arrows are showing current flow, small circles are showing supply inputs.
Cyan circle are showing high-current part of the amp, OPS. Small circles with green X mark are high-current unregulated supply inputs, small circles with yellow dots are high-current outputs.
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Re: Understanding Beta

Postby BesPav » January 17th, 2017, 10:01 am

Now some thoughts, that are different than Ti's.

Beta24's PCB specific routing, at my sight, have very good features in dedicated groung plane and two huge power planes.

But, again, at my sight, have drawbacks.
Magenta circle of the heatsink surface are not used:

Image

And we take in mind this:
Image

And this:
http://www.aavid.eu/thermal-tools/temperature-correct

And some talking with manufacturers, which claimed that dissipation factors are shown for ~80-100 degree difference between heatsink surface and air.

And outboard high-current loops like this:
Image


Some thinking, math, discussing - and we choosed to try Beta24 with 2U 400 mm Pesante Dissipante case from Modushop.

All heavy heating elements well to be located at common heatsink. And that OPS layout was borned:
Image
Red line in first thoughts was a place to perpendicular mesonine IPS/VAS board.

Next routing shows a possibility to exclude outboard loops by fastening high-current outputs and inputs at a local points like this:
Image

That layout provides two different paths for quiescent and signal currents like shown (thin red - quiescent, thick yellow - signal)
Image

Also we choosed to:
1. Completely remove thermal barriers in the solderpoints, this is because thick TO-247 legs anyway unable to solder by cheap steel-tip iron. Good irons like ERSA, Hakko, Goot and oldish-copper-tip can solder that legs anyway with easy.
2. Use dual-layer 100 um (~3 Oz) copper-foil PCB process.
3. Provide windows in soldermask for adding onboard strengthening.
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Re: Understanding Beta

Postby BesPav » January 22nd, 2017, 9:24 pm

Next Beta24's feature is a comparatively low output resistance.
There are two main reasons - high transconductance output devices and moderate feedback depth.

The main component aren't covered is a wire resistance.
Image

I was very interested to apply slightly different wiring scheme with feedback taken not at the Beta's PCB, but from output binding posts or even speaker binding posts like this:
Image

Ti's reasons not to do this are clearly, this is DIY and one mistake in wiring would guarantee speakers will be blown away by full Beta's power.
No one conventional civil speakers can resist impact of ~60 Volts DC.
I know some, but they are very uneven.
https://m.youtube.com/watch?v=rEhr8uBO_gQ

The second way to reduce effective output resistance, as comprehensive ones can say, is to shorten wires as possible. Say 0,5 m. So we choosed to provide construction in monoblocks. Less ground loops, less crosstalk, but more priced case and two trafo's.

Backing to the build.
In the 21s century we can use mostly SMD components, so our PCBs contains most of the 1206/melf0204 cases.
Comparatively expensive CRDs was replaced by cheap mmbfj201.
And we get little 4-layer small-signal IPS/VAS/CMFB PCB:
Image
And both:
Image

Red - IPS/VAS shoulders, black - overall feedback, cyan - CMFB.
Image
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Re: Understanding Beta

Postby BesPav » January 23rd, 2017, 1:42 am

Now some words about heat dissipation margins.

This question are oftenly forgotten and some developers doesn't take proper care about.

Let's check.

Worst case of load.
Image

Resonant freq ~60 Hz.

Let's test Beta24 at 240 Hz with +-40 Volts of output voltage.

In this case between load current and load voltage will be a near 40 degree phase lag.
Blue line - output voltage(left scale),
Green line - output current(right scale).
Image

Now dissipation (one quarter of OPS are shown)
Red line - lower MOSFET
Magenta line - higher MOSFET
Cyan line - OPS power resistor
Image

Now we can see dissipation peaks at ~120 Wt on both upper and lower MOSFETs.
So Ti's choice of ~150 Wt MOSFETs are not excessive for 4-Ohm load class.
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Re: Understanding Beta

Postby BesPav » January 23rd, 2017, 7:48 am

Now, keeping in mind our much less heatsinks, we choosed to provide the lowest possible thermal resistance between semiconductor crystal and free air.

Crystal-substrate out of our control, but substrate-isolation pad and isolation pad-heatsink can be improved.

First, isolation pad.
There are two main features - thickness and thermal conductivity.
Thick isolation pad gives lower parasitic conductance and lower conductivity.
So we choosed to use 1 mm thick Aluminium Nitride ceramics instead of usual Nomacone or Aluminium Oxide.
Custom 55x65 plates was ordered and you would feel its hign thermal conductivity at your fingertips.

Next - heatsinks.
Usually, Modushop heatsinks are anodized in black.
I ask my friends in State Optical Institute to polish heatsink surface with maintaining overall geometry and flatness. So they was touched by craftman's hands and state-of-the art machines:
Image

Power transistors will be mounted with Aavid Max Clip system clips and corresponding mounting rail:
Image
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Re: Understanding Beta

Postby cobretti » January 23rd, 2017, 12:19 pm

I would like to see both power planes feeding the large caps on the outside the PCB. Imagine you short the cap and all the current is handled by the through hole and basically the thickness of the copper traces surface area, which is very small.
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Re: Understanding Beta

Postby BesPav » January 23rd, 2017, 9:14 pm

Hi, Cobretti, your comments are welcome!
cobretti wrote:I would like to see both power planes feeding the large caps on the outside the PCB.


Of course, power supply discussion are coming. ;)
Image

cobretti wrote:Imagine you short the cap and all the current is handled by the through hole and basically the thickness of the copper traces surface area, which is very small.


Not clearly so.
First of all, flowing current are limited mostly by heat dissipation.
For standalone wire more-or-less safe operating area are defined by 8-10 A/sq.mm.
At the PCB surface numbers are differ, say for simplicity 1 A/1mm width of 35 um copper layer. This is because of good heat transfer from the copper to a FR4 bulk.
In our case copper traces can be empowered by 14-16 AWG wire straightly from the nearest electrolytic capacitor's leads to the MOSFET's leads. Small film capacitor of 1 uF are placed directly at the leads providing as short as possible high-frequency current path.

There we need to talk something about decoupling. The most of techniques are taken from HF transeivers, but can be easily adopted to audioamps.

Let's see worst case, decoupling capacitors are far from OPS.
Positive and negative currents are drawed by red and blue lines.
High-current high-frequency signals runs through huge loop and covers around a half of the PCB.
Image
Improper layout, bad decoupling technique.

Now, better case. Supply decoupling caps are placed as close as possible to the OPS and choosed layout provides comparatively small loops.
Image
Decoupling caps have intrinsic parasites, such as ESR and ESL, so proper decoupling in the case of high-current high-frequency signals must be designed with different kinds and nominals of capacitors.
Say, 1 uF film (or ceramics) straight to the leads (or as close as possible), small 220 uF can very near, medium can of 6.800 uF not far and huge 33.000 uF can more or less far.
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Re: Understanding Beta

Postby BesPav » January 31st, 2017, 10:55 pm

Now, some thoughts about transformers.

Let's assume, toroidal trafo.

Most of the suppliers have old winding machines. Basical principle of winding are shown on this video:
https://m.youtube.com/watch?v=oBdJvT7tpSM

There are one meaningful problem - direction of winding.

All old winding machines turns core in one direction and in our medium-power range 200-800 Wt trafo will consist of 4-6 layers of primary AC mains winding and some secondary windings.

Layers will be winded in the same direction like this:
Image

But having 4-6 layers we would have 4-6 turns of primary winding in the plane of the core.
This winding scheme can't be diagnosed without loading trafo because there are no active current through primary winding.
In the actual amplifier build there will be signal-correlated fluctuations in the trafo's outer magnetic field. Not a pulsed constant dissipation field around it, but directed field at the center axis of the toroid. Your case, being conductive, will provide counter-direction field and, of course, different potentials at the surface of the case panels.

So, more sophisticated way is not fight with problems, but reject them.
We just need to change winding direction between layers like this:
Image

Classical situation again, if you want best things - you better to do it by yourself.


Classical II and III trafos are less affected by this, and have other benefit - very low parasitic capacitance between windings.
To make this properties better we can increase substrate thickness like this (marked as red line):
Image
So, primary winding will be at the center and two secondary windings at the top and the bottom of the core window.

With the toroid core we can place secondary windings in the sections of the whole core perimeter.

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Re: Understanding Beta

Postby Alan0354 » September 24th, 2019, 4:07 pm

BesPav wrote:Backing to understanding.

At last step we get our signal effectively referenced to the ground.
Now we just need to bufferize it.

What bufferize is?

This is only providing all needed current to the load with keeping output voltage as close to the input.

First approach to the very effective buffering was offered by the Bart Locanti in the last 1960's. Here are the original article:
http://leachlegacy.ece.gatech.edu/papers/tcir/tcir.pdf
Or some words about here:
http://leachlegacy.ece.gatech.edu/lowtim/output.html
Also very good related reading can be founded here:
http://hifisonix.com/ovation-e-amp/

Modern transistors have the very higher hFE (beta) than in 1970's, so effective current gain can be like 10.000.000 (multiply beta's of BC550*2SC4793*2SC5200)

The more current gain have the OPS - the lower loading of the VAS - the lower distortion.

There are unspoken rule - all gain stages must work at stable current or stable voltage.

So there are some OPS design goals:
1. Relatively high input resistance
2. Relatively low input capacitance
3. Relatively high current gain
4. Relatively easy achieved thermocompensation
5. Relatively high corner frequency (widebandness)
6. As high as possible Safe operating area (SOA)

Now we have great idea of cascode, some words from Papa Pass here:
https://passlabs.com/press/cascode-amp-design

Let's return to the Beta24's OPS.
It's very sophisticated.
It is not statically cascoded, but dynamically and capable of near rail-to-rail OPS supply output.
Image

Widebandness are achieved by effective neutralising of input capacitance. Yes, IRFP140 have huge ~2000 pF, but upper and lower transistors provide stable voltage to the centered ones. So, there are no voltage change - no capacitor charging/discharging - virtually no capacitance. In terms of hightening of widebandness we are limited mostly by Zeners dissipation and parasitic inductance of the gate traces.

Ultrasonic pole frequency can be easily tuned by gate resistances as gate-stoppers.

Current gain are very high (not to say infinite) and limited mostly by wire resistances and SOA of the rugged MOSFETs.

Thermocompensation was discussed here:
http://www.amb.org/forum/simulating-bet ... tml#p32670
Having ~10-15 mV/degree sensitivity and 15-20 A/V transconductance with idle current ~200 mA or 1,4 A the Beta24's OPS are thermally stable.

Bias circuitry are loaded on relatively high 1 uF capacitor, have a corner frequency at about of ones of Hertz and can't oscillate in any conditions.

SOA are very good based on series connection of the transistors and dividing actual OPS supply rails voltage between them. Even with realistic 45-50-55 degree of current phase lag this OPS can dissipate large amount of heat and provide amperes and tens of load current in short bursts.


I have been reading the OPS, I read what you said that Q37 and Q38 is to provide a constant voltage to Q33 and Q34 respectively in order to lower the input capacitance of the OPS stage. That I agree. BUT seems like it's a steep price to pay to make it easier for the driver stage to drive. This is my reasons, I would like to hear some feedback:

1) Seems like it's much simpler to put in a driver stage, something like an emitter follow stage to buffer Q13 and Q14.
2) The way the design, you have to have a higher V+ and V- in order to give the head room for this "Cascode like" stage to work in order to lower the input capacitance. In term of heat dissipation, you have more heat generated in this design than a simple source follower with emitter follower buffering the Q13 and Q14. You need some headroom from this "Cascode like" OPS.
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