The ζ1 Audio Widget asynchronous USB-I²S module

Design integration

Despite many pins, the ζ1 is easy to integrate into a new design. There are only a few pins of interest. Aside from the many ground pins (to provide a solid ground connection to the main board), most other pins are there for historical reasons, and are unused when implementing a DAC. They do not need to be connected to anything on the main board.

The following diagram shows the pin-out of the ζ1 module and the table provides brief descriptions of the pins.

Pin Name I/O Description
2, 27 VDD_3V3 O Regulated 3.3V DC output
5 NSRST I External RESET switch (active low)
28 VDD_5V0 I 5V DC power for the ζ1
32 MCLK_P48_N441 O Master clock select
34 MCLK_441 I Master clock input for 44.1KHz sample rate and multiples
36 MCLK_48 I Master clock input for 48KHz sample rate and multiples
52 PROG I External PROG switch (active low)
53 VDD_SENSE I Bus-powered or self-powered configuration
54 VBUS_EN O Enable pin for external voltage regulators
56 DA_SCLK O I²S SCLK (bit clock)
58 DA_SDATA O I²S DATA (serial data)
59 DA_LRCK O I²S LRCK (word clock)
68 GPIO_08_LED1 O External LED (UAC1 mode, active high)
69 GPIO_05_LED2 O External LED (UAC2 mode, active high)
0, 7, 11, 14, 17, 21, 26, 30,
31, 33, 35, 37, 46, 49, 55, 57,
60, 61, 63, 65, 67, 75
GND - Ground

The following sections describe typical application information by functional groups. They do not reflect all possible uses of the ζ1 module.

Logic level

All input and output logic for the ζ1 are 3.3V level. These include MCLK_P48_N441, MCLK_48, MCLK_441, VBUS_EN, DA_SCLK, DA_SDATA, DA_LRCK, GPIO_08_LED1 and GPIO_05_LED2. If the main board circuitry operates at a different logic level, the appropriate level-shifter circuitry should be used (with a possible exception of the two LED lines).

Power supply

The ζ1 can be configured to operate in bus-powered or self-powered modes.

Bus-powered mode

In this mode, The ζ1 (and most likely the main board) are powered by the USB host. 5V DC power comes in through the USB socket, and is also used by the ζ1 MCU to detect USB cable connect/disconnect status. The USB 5V does not directly power anything on the ζ1 module. Instead, it is routed to VBUS (board connector pin 29). The main board should provide an anti-inrush circuit with soft-start characteristic on this line, and feed the output of the soft-start back to the ζ1 at VDD_5V0 (board connector pin 28). This 5V line after the soft-start can also be used (and possibly converted to other voltages by voltage regulators or converters as needed) to power other circuitry on the main board, such as the DAC, oscillators and other logic.

This soft-start is needed because the USB specification requires that no more than 10µF of capacitance be placed directly across the 5V and ground lines. Most circuits would have much more capacitance than that. As the USB cable is connected, a surge current would occur to charge the capacitor(s), and may damage the USB host. Having a soft-start circuit would prevent this from happening.

The VDD_5V0 power is regulated down to 3.3V DC by a LDO voltage regulator onboard the ζ1 (U2), and provides power to all circuitry on the module. This 3.3V power is also available at VDD_3V3 (board connector pins 2 and 27), which could be used by the main board circuitry.

VBUS_EN (board connector pin 54) can be used as an enable signal for voltage regulators on the main board. The ζ1 asserts this line (active high) when the MCU is powered up and started running its firmware. Using this line to enable external voltage regulators ensure proper power-up sequencing.

VDD_SENSE (board connector pin 53 should be connected to ground via a 10KΩ resistor. The ζ1's USB descriptor data will show as bus-powered with 500mA maximum power when wired in this configuration.

Since the maximum current draw from a USB port is 500mA, care should be taken to account for the total power usage in all parts of the circuit, under the worse-case scenarios. The ζ1 itself draws less than 100mA.

Self-powered mode

In this mode, the ζ1 and the main board do not get their power from the USB host. No soft-start circuit is required. The only function of the USB 5V is to provide the ζ1 MCU with USB cable connect/disconnect status. VBUS (board connector pin 29) is typically unused on the main board.

The main board provides the 5V DC power for the ζ1, through VDD_5V0 (board connector pin 28). Obviously, this 5V power should not be from a voltage regulater that's enabled by VBUS_EN (board connector pin 54).

VDD_3V3 (board connector pin 27) and VBUS_EN have the same function as in the bus-powered configuration.

VDD_SENSE (board connector pin 53 should be connected to VBUS_3V3 via a 10KΩ resistor. The ζ1's USB descriptor data will show as self-powered with 10mA maximum power when wired in this configuration (with firmware version zeta1_100_fw_20150826 and later).

Master clocks

In a asynchronous USB DAC, the DAC's master clock is the timing reference for the entire chain. Most modern DACs require that the master clock to be a power-of-2 multiple of the sample rate (such as 128fs, 256fs, 512fs, etc.). To support sample rates that are a multiple of 44.1KHz, an oscillator frequency of 22.5792MHz is often used, as well as a 24.576MHz oscillator for multiples of 48KHz. This results in the following multipliers:

Sample rate 44.1KHz 48KHz 88.2KHz 96KHz 176.4KHz 192KHz
Master Clock
22.5792MHz 512fs - 256fs - 128fs -
24.576MHz - 512fs - 256fs - 128fs

Some DACs use different master clock frequencies, but the same principle applies. In all cases, to support all the standard sample rates that the ζ1 is capable of, two master clock oscillators must be provided on the main board.

Note that despite that ζ1 theoretically also supports 132.3KHz and 144KHz sample rates, these do not actually work with most DACs because the 22.5792MHz and 24.576MHz master clocks are not a power-of-2 multiplier for these sample rates.

The ζ1 module does not generate any master clock. It is assumed that the main board provides what is needed for the DAC. For best performance, the oscillators should be physically located as close to the DAC as possible with short PCB traces.

The ζ1 provides a mechanism for automatically selecting the appropriate external oscillator based on the sample rate, via the MCLK_P48_N441 line (board connector pin 32). When the audio data sample rate is a multiple of 44.1KHz, this line is low. It goes high when the sample rate is a multiple of 48KHz. In the diagram below, the example circuit uses this line to drive the enable pin of the two oscillators, one of them through an inverter. Thus, only one of the oscillators is enabled at a time.

When an oscillator is not enabled, its output becomes high-Z, therefore the two oscillators' outputs can be wired together with small value resistors, and connected to the DAC's master clock input.

The ζ1 also needs the master clock as a timing reference. The I²S output bit and word clocks are derived from the master clock, and the asynchronous rate-feedback mechanism also use it. The MCLK_441 and MCLK_48 lines (board connector pins 34 and 36) are used to feed the master clock back to the ζ1. The MCLK_441 line is from the 22.5792MHz oscillator and the MCLK_48 is from 24.576MHz. The ζ1 has an onboard multiplexer that will select from one of these based on the sample rate.

Note: The master clock frequency must first be divided by 2 before being fed back into the MCLK_441 and MCLK_48 pins. If your oscillators are not of the same frequencies as the example circuit, then the division ratio will also need to be different.

In the example circuit below, the master clock is sent through divide-by-2 logic and fed to both the MCLK_441 and MCLK_48 pins. This is done because there is a single line for the master clock with the appropriate frequency for all supported sample rates. So it doesn't matter which of these lines are selected by ζ1's onboard multiplexer, it will get the correct frequency.

The following diagram shows an alternative wiring scheme where the two oscillator outputs are not connected together. This may be needed for certain applications. In this case, there are separate divide-by-2 logic gates for the two frequencies and they are fed back to the ζ1 MCLK_441 and MCLK_48 lines individually.

I²S output

The I²S output are the DA_SCLK, DA_SDATA and DA_LRCK lines (board connector pins 56, 58 and 59). The diagram below illustrates the I²S lines connected to a DAC. The recommended resistor values are around 33Ω.

External LEDs

When the ζ1 module is in UAC1 mode, GPIO_08_LED1 is high and GPIO_05_LED2 is low. In UAC2, the reverse is true. These two lines can be used to drive external LEDs to display the current running mode. External current limit resistor(s) for the LEDs should be provided on the main board. The diagram shows two options, Option 1 uses a shared resistor between the two LEDs, whereas Option 2 uses individual resistors. A value of 560Ω to 680Ω is recommended.

Note that discrete LEDs are shown in the diagram below, but a common-cathode bi-color LED could also be used. Since these lines are 3.3V logic, LEDs with a forward voltage of less than 2.5V should be used. This rules out certain colors. Use red for UAC1 and green for UAC2 to be consistent with AMB's DAC implementations and documentation.

External switches

The onboard RESET and PROG switches can be replicated on the main board (for external access when installed in an enclosure). These are done via board connector pins 5 and 52, respectively. These lines are active-low (i.e., short to ground when switch is pressed). Momentary-contact SPST switches should be used.

Board interface connectors

The 2mm-pitch single-row pin receptacles and headers are not included with the ζ1 module. Their part numbers are listed below. Please see the Parts list section about joining the female receptacles to make the correct number of positions.

Qty. Description Digi-Key part number
1 Sullins NPPN251BFCN-RC 25P 2mm-pitch single-row receptacle S5751-25-ND
1 Sullins NPPN061BFCN-RC 6P 2mm-pitch single-row receptacle S5751-06-ND
3 Sullins NPPN151BFCN-RC 15P 2mm-pitch single-row receptacle S5751-15-ND
1 Sullins NRPN311PAEN-RC 31P 2mm-pitch single-row pin header S5800-31-ND
1 Sullins NRPN301PAEN-RC 30P 2mm-pitch single-row pin header S5800-30-ND
1 Sullins NRPN151PAEN-RC 15P 2mm-pitch single-row pin header S5800-15-ND

AMB's convention is to mount the female receptacles on the bottom of the ζ1 module, and the male headers on the top of your main board.

Main: ζ1 Main | Prev: Firmware | Next: Miscellaneous