The γ24 high performance DAC core

Design integration

This section is of interest primarily to DIYers who might want to use the γ24 as the core of their own DAC design.

The γ24 is easy to integrate into a new design. There are only a few pins of interest. A good knowledge of digital audio is assumed, as is the ability to develop MCU firmware to control devices, especially via an I²C bus. You should also read the SRC4392 and WM8741 datasheets for details about their register maps and programming information.

The following is a diagram of the γ24 pin interface, and a table with descriptions of each of the pins. All logic levels are 3.3V-based.



Pin #NameI/ODescription
1, 6, 15-17, 21, 24, 25, 27, 29, 32, 34, 36, 41-53, 56-58, 62, 63, 66, 69, 72GND-Ground
2PCMDSDI PCM/DSD mode select
  • When this pin is driven low (0V), the I²S input lines are deemed to carry PCM data and routed to the SRC4392's serial port B, which is set up as an I²S slave.
  • When this pin is driven high (3.3V), the I²S input lines are treated as DSD and routed directly to the Wolfson DACs, bypassing the SRC4392. The following table shows the signal mapping:

    I²S (PCM mode)DSD
    I2SDATARight channel DSD data
    I2SLRCKLeft channel DSD data
    I2SSCLKDSD64CLK
3I2SDATAI I²S input

These are typically used to implement a USB audio input, via a USB-I²S bridge module such as the ζ1. Other I²S sources supporting 24 bits and up to 192KHz sample rate data could also be used.
  • I2SDATA - data
  • I2SLRCK - word clock
  • I2SSCLK - bit clock
These signals are handled differently in DSD mode (see pin 2 above).
4I2SLRCK
5I2SSCLK
7-14RXn+, RXn-I Four AES3-compliant fully-differential digital inputs

Where n is an input number (1..4). These are connected to the SRC4392 pins of the same names.
18VREFO Logic level reference

The γ24 provides 3.3V DC via this pin to the main board. It could be used as a reference voltage for a logic level translator, if needed. The main board should not draw more than 20mA of current from this pin.
19, 20, 22, 23N/C- Unused pins
26LOCKO DIR lock

Connected to the SRC4392 pin of the same name. This pin is an open drain output, pulled low when the DIR's PLL has a lock on the input stream.
28RDYO DIR ready

Connected to the SRC4392 pin of the same name. This pin is an open drain output, pulled low when the DIR is ready.
30, 31SCL, SDAI I²C bus

For software control of the SRC4392 and WM8741s. The I²C addresses are as follows:
DeviceI²C address
SRC43920x70
WM8741 (left channel)0x1a
WM8741 (right channel)0x1b
These lines have 2.7KΩ pull-up resistors on the γ24 board.
33INTO Interrpt pin

Connected to the SRC4392 pin of the same name. This pin is an open drain output, pulled low when an interrupt occurs. Typically connected to the MCU to trigger an interrupt service routine.
35RESETI Board reset

Pull this pin low to hold the board in reset. The onboard voltage regulators are also disabled, cutting power to most parts. When this pin is set high, the board powers up and go into the initial power up default modes and ready for software control.
37-40GPOnO Four programmable general purpose output ports

Where n is the port number (1..4). Connected to the SRC4392 pins of the same names.
54, 55L+, L-O Left channel differential analog output

This is the direct analog output from the left channel WM8741 DAC.
59, 60TX-, TX+O Fully-differential AES-compliant digital output

Connected to the SRC4392 pins of the same names. An on-chip line driver eliminates any need of additional buffering.
61AESOUTO Single-ended CMOS-buffered digital output

Connected to the SRC4392 pin of the same name. This is typically connected to a fiber optic (Toslink) transmitter module.
64, 65R+, R-O Right channel differential analog output

This is the direct analog output from the right channel WM8741 DAC.
67AVSSI Analog negative power supply input

The main board should provide clean, regulated -10V DC to this pin.
68AVDDI Analog positive power supply input

The main board should provide clean, regulated +10V DC to this pin.
70, 71DVDDI Digital power supply input

The main board should provide clean, regulated +5V DC to this pin.

Basic application

The following block diagram illustrates an example application of the γ24 DAC core. This is a basic yet high quality DAC with one coax input and one optical input, and RCA unbalanced outputs. The analog output stage must perform balanced-to-unbalanced conversion. This diagram assumes that all logic levels are 3.3V. The power supply is not shown.



For a more advanced application, please see the γ3 DAC.

A note about the γ3 firmware

The γ3 firmware for the LCDuino-1 display I/O processor was developed specifically for the γ3 system and must be modified for different applications. If you will be using portions of the γ3 firmware in your own code, be sure to read the GNU General Public License information.


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