The γ2 Compact High Performance DAC

Schematic diagram

The following is the schematic diagram of the γ2 DAC. Parts values are not shown. Please see the Parts list section for more details.



Here is the schematic diagram in PDF format (70KB).

Circuit Description

Board connectors

J1-J5 are the connectors that allow the γ2 to plug into their counterparts on the γ1 board. The γ2 board serves as the "bridge" between the γ1's USB and DAC board sections when the boards are mated. J1 and J5 contain the 5V power and ground lines whereas J2 and J4 carry the I²S signals (MCKI, LRCKI, BCLKI, DATA and ground). If the γ1 is a Full (A), S/PDIF-only (E) or Full++ (F) configuration, the I²S DATA line is on J3 pin 2 rather than on J2 or J4. The γ1's JP1D pin 2 should be populated with a pin header for connection to J3. γ2 assumes this configuration as the default, for the γ1 Lite (B) or USB-to-I²S (D) configurations, γ2's J3 should not be populated, and JP1 should be shorted to bridge the I²S DATA line.

Voltage regulation

The 5V power is regulated by two low-dropout voltage regulators U1 and U2 to 4.5V and 3.3V, respectively, for the separate analog and digital supply rails. Ultra-low ESR conductive polymer capacitors C3 and C6 ensure proper voltage regulator performance. Ferrite beads L1-L5 are used for additional filtration against noise. Each circuit block has its own ferrite bead. Supply decoupling is provided by X7R multilayer ceramic capacitors at each chip's supply pin.

Upsampling (optional)

If the U4 ASRC chip is populated, the I²S signals are routed to it via R1, except the master clock (MCLK). MCLK is locally-generated by X1, an ultra-low jitter 24.576MHz CMOS oscillator. The re-clocked and upsampled I²S bus are the signals MCLK, LRCK, BCLK and D. U3 is a chip reset manager to ensure proper start-up of the ASRC chip when the power is applied.

The SRC4192 and AD1896 ASRC chips are equivalent and pin-compatible, either one could be used in the γ2 with excellent results.

The upsampling feature may be omitted by not populating R1, C7, U3, U4 and X1, and shorting the JP2-[1-4] jumpers. Note that the JP2 jumpers should not be used to bypass the ASRC if U4 is installed.

Digital-to-analog convertor

The upsampled I²S bus is connected to the U5 Wolfson DAC chip via R2. The DAC is configured to run in "hardware mode", so that it does not require microcontroller assistance to function. The chip is also set to clock its internal digital filters at 256 times the sampling rate, which (if the ASRC is installed) is supplied by the onboard X1 ultra-low jitter CMOS oscillator. See the schematic diagram and the DAC chip datasheet for details on how the other configuration pins are set up.

The SW1 and SW2 switches are for digital filter selection and anti-clipping mode, respectively. See the tech highlights section for a description of these functions.

The WM8741 and WM8742 have identical pin-outs and functionality, whereas the WM8740 is "mostly" pin-compatible with some notable exceptions, two of which affect their use in the γ2:
  • WM8741 and WM8742 have an internal power-on reset manager but WM8740 does not. The U6 reset manager chip should only be populated if the WM8740 is used.
  • WM8740 does not have selectable digital filters in hardware mode, nor does it have the anti-clipping feature. Thus, if WM8740 is used, SW1 and SW2 should not be installed, and the FSEL and ACLIP signals should be shorted to ground.

Analog output stage

The Wolfson DAC chip provides differential analog voltage outputs for each channel, which is sent to the analog output stage comprised of U7, a low-noise rail-to-rail precision dual opamp, and its surrounding parts. Two opamp options have been chosen for this stage, the OPA2365 or the AD8656.

U7 serves triple duty as balanced-to-unbalanced converter, analog low pass filter, and output buffer. Rather than simply using the the non-inverting signal for each channel (and discarding the inverting one), γ2's balanced-to-unbalanced converter retains high common-mode rejection (CMR), ensuring that the full S/N ratio and distortion performance of the DAC to be realized. It also allows complete differential output voltage swing.

The second-order (12dB per octave) analog low-pass filter with corner frequency of 100KHz removes out-of-band noise and artifacts. This is important if the DAC is to be used with a wideband, high-speed amplifier. Polypropylene film capacitors are used for the filters. The output buffer provides low output impedance and high current drive capability. If the AD8656 opamp and 470µF output coupling capacitors are used, γ2 could drive low-impedance headphones directly.

The DAC is direct-coupled to this stage, thus the opamp is biased to VADD/2 to each of its inputs. Since the opamp is also powered from the single analog supply, its output DC offset is also at VADD/2 at idle, and requires output coupling capacitors (C20, C26) prior to the output jacks. Several types of audio-grade capacitors are selected as options for these, as well as film bypass capacitors (C19, C25). Due to the low analog supply voltage, the "gain" of this stage is set to 0.7, to ensure that the signal will never clip at 0dBFS.

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