The β22 Stereo Amplifier

Schematic diagram

The following is the schematic diagram of each β22 amplifier board. See the Parts list section for details about parts selection.

Click the schematic below to see a larger version with all parts annotated.



Here is the detailed schematic diagram in PDF format (25KB).

Circuit description

Like many amplifiers, the β22 consists of three main stages. The first is the input stage. This is followed by the voltage amplification stage, and then the output stage.

The input stage is comprised of a JFET complementary differential amplifier Q1-Q4. The 2SK170 and 2SJ74 JFETs provide very high input impedance, and are characterized by very low noise. The upper and lower pairs are cascoded by BJTs Q5-Q8. These cascode transistors are dynamically biased by the zener voltage reference D1 and D2. The zener current is regulated and isolated from the supply rails by constant current sources CR1 and CR2. The two differential pairs feed directly into each other and acts as the current source for each other. The bias for this stage is adjustable by trimpot CR1 which also scales the bias for the next stage. The quiescent current through each side of the differential pair is 2mA. This is an optimum setting for low noise.

The output DC offset is adjustable via trimpot VR3. The voltage reference for this trimpot comes from two small signal diodes D3 and D4. The current through these diodes are regulated by constant current sources CR3 and CR4.

The VAS stage is also a complementary differential topology with cascoding, except it is BJT-based and inverted compared to the input stage. Q9-Q12 are the differential pairs and Q13-Q16 are the cascodes. Similar to the input stage, the cascode transistors are biased by zeners fed by constant current sources. In this case each side of the pair is biased individually. The four-way differentially-driven VAS stage provide additional distortion-cancelling properties. C2-C4 are compensation capacitors to tailor the high frequency bandwidth and phase margin for stability. The quiescent current through each side of the differential pair is about 15mA, providing ample charge for the output stage MOSFET gates.

Q17 and Q18 form a complementary Vbe multiplier circuit to provide the adjustable (via trimpot VR2) bias voltage for the output stage.

The output stage is a source follower comprised of MOSFETs Q21 and Q22, and cascoding MOSFETs Q23 and Q24. These are the same proven IRFZ24N and IRF9Z34N as used in the M³ amplifier. The cascoding MOSFETs are again dynamically biased by zener diode voltage references. The zener current is a high 15mA (provided by PN4392 JFETs Q19 and Q20 acting as constant current sources), also to provide ample MOSFET gate charge. The quiescent current through the MOSFETs is set at 160mA.

All BJTs used in the amplifier are the low noise, high-Hfe BC550C and BC560C devices. These transistors also have low Cob and extended Ft at 250MHz.

As noted above, each of the three stages are dynamically cascoded, which greatly linearizes the transfer characteristics of the amplification transistors. This is because the voltage across the amplification devices are held constant. Cascoding also reduces the input capacitance of the amplification devices, increasing slew rate and bandwidth. Additionally, cascoding divides the voltage seen by the devices to reduce their heat dissipation.

Every stage also operates in class A, flowing constant current. The constant current, constant voltage condition make the amplifier extremely linear even prior to the application of global negative feedback.

With the exception of the output MOSFETs, every other part of the circuit gets their power through a capacitance multiplier on each rail. In conjunction with heavy use of constant current sources, the amplifier posses very high PSRR (power supply rejection ratio).

The open loop gain is set at approximately 56dB (about 650x), compared to many IC opamps which have open loop gain of 120dB or higher (1000000x +). This allows only a moderate amount of global negative feedback to be applied to further reduce the distortion, lower the output impedance and extend the bandwidth.


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